This paper looks into prospects of pre-timed arterial traffic control systems for cities with limited infrastructures. The methodologies for designing a pre-timed arterial traffic controller system were researched. A prototype designed and implemented in Field Programmable Gate Arrays (FPGA) is presented. Dar es Salaam Roads have been used to provide data for the design and implementation whereby the neighboring road intersections within a logically computed radius of less than 250m qualified for pre-timed arterial traffic controller. One intersection is a master and the remaining ones act as slaves. Using Very High Speed Hardware Descriptive Language (VHDL), an algorithm has been developed for coordinating adjacent traffic signals along the arterial roads. The use of VHDL enabled the algorithm to be implemented and tested in Xilinx Spartan 2E Field Programmable Gate Array (FPGA) that functioned and served the purpose of real-time simulation of Arterial Traffic Controller.Sida-SAREC