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Low voltage ride through enhancement for wind turbines equipped with DFIG under symmetrical grid faults

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dc.creator Justo, Jackson J
dc.creator Mwasilu, Francis
dc.date 2019-02-04T05:19:41Z
dc.date 2019-02-04T05:19:41Z
dc.date 2018-12-31
dc.date.accessioned 2021-05-07T07:55:14Z
dc.date.available 2021-05-07T07:55:14Z
dc.identifier (Tanz. Journ. Engrg. Technol
dc.identifier 2619-8789 (electronic)
dc.identifier 1821-536X (print)
dc.identifier http://hdl.handle.net/20.500.11810/5031
dc.identifier.uri http://hdl.handle.net/20.500.11810/5031
dc.description In modern power systems with significant penetration of wind-turbines (WTs), improvement of low voltage ride through (LVRT) capability of WTs equipped with doubly-fed induction generators (DFIGs) is an important issue. Thus, this paper proposes a low voltage ride through (LVRT) strategy, which comprise of a capacitor connected in series with an inductor both connected in parallel to a resistor. The configuration is then connected to a small series resistor via a pair of antiparallel-Thyristors. The circuit and its switching control scheme of the proposed LVRT circuit are designed to: minimize the transition times, maintain the RSC connection to the rotor-windings, and reduce oscillations of dc-link voltage. In this case, the capacitor is entitled to eliminate ripples generated in the rotor voltage while the inductor reduces the ripple in rotor current. Different fault conditions were studied to validate the performance of the proposed scheme using MATLAB/Simulink platform. Comparative results and analysis are presented with conventional LVRT strategies.
dc.description N/A
dc.language en
dc.publisher Journal of Engineering and Technology, TJET
dc.relation 37;2
dc.subject Doubly-Fed Induction Generator (DFIG), Fault Ride Through (FRT), Low Voltage Ride Through (LVRT), Rotor Side Converter (RSC), and Wind Turbines (WTs).
dc.title Low voltage ride through enhancement for wind turbines equipped with DFIG under symmetrical grid faults
dc.type Journal Article


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